Ashish Bajaj
Vice President Edge AI Inference & Wireless Wi-Fi Proprietary Sub-GHz RAIL at Silicon Labs
Hyderabad, Telangana, India
Summary
👤
Senior🎓
Top SchoolAshish Bajaj is a seasoned engineering leader with 20+ years building low-power SoCs, multimedia DSP firmware and edge AI/wireless platforms, now leading a 150+ multi-site organization at Silicon Labs focused on Wi‑Fi, RAIL, Sub‑GHz and TinyML. He combines deep hands-on chipset and power-optimization expertise from Qualcomm with founder experience—having scaled Elear Solutions and led COCO, a smart-home edge platform, toward an acqui‑hire. His work drives a $5B+ design-win pipeline by cutting integration time, improving power/throughput/latency, and raising release quality through a scorecard-led approach to Innovation, Customer Success and Software Quality. Comfortable seeding teams and products from zero to market, he’s equally committed to open source and plans to release COCO publicly when practical.
11 years of coding experience
15 years of employment as a software developer
Master of Science (MS) Electrical and Computer Engineering, Master of Science (MS) Electrical and Computer Engineering at Georgia Institute of Technology
Github Skills (71)
stream-wrapper10
raspbian10
pug10
linux9
broker9
windows9
eclipse9
command-line-tool9
angular-app9
yeoman9
yeoman-generator9
full-stack9
mosquitto9
mongodb9
angular8
Programming languages (6)
Github contributions (5)
ashishbajaj99/mic
Jan 2016 - Mar 2019
A simple stream wrapper for arecord (Linux (including Raspbian)) and sox (Mac, Windows). Returns a Passthrough stream object so that stream control like pause(), resume(), pipe(), etc. are all available.
Contributions:34 commits, 10 PRs, 26 pushes in 3 years 1 month
linuxraspbianstream-wrapperwindows
ashishbajaj99/data-structures
Nov 2015 - Nov 2015
Contributions:19 commits, 26 pushes, 1 branch in 6 days
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