Summary
Chaeeon Lim is a research-oriented software engineer and current MS student at UT Dallas with eight years of experience applying deep learning to real-world systems, especially FPGA-accelerated inference. At Future Design Systems he optimized quantized YOLO for 1080p FPGA deployment (10x throughput improvement) and built sensors-to-cloud pipelines that enabled real-time processing and improved detection accuracy. Skilled across embedded interfaces (PCIe, USB, Modbus), multiprocessing, and image/3D OCT preprocessing, Chaeeon blends low-level systems engineering with ML model tuning to reduce latency and false positives. A former Army sergeant and teaching assistant, he pairs discipline and pedagogy with hands-on research engineering, and continues exploring sparsity and NLP as part of his graduate studies.
8 years of coding experience
3 years of employment as a software developer
Master of Science - MS, Computer Science, Master of Science - MS, Computer Science at The University of Texas at Dallas
Bachelor of Science in Engineering, Computer Science, Electronics Engineering, 3.63/4.50 (equal to 90.3), Bachelor of Science in Engineering, Computer Science, Electronics Engineering, 3.63/4.50 (equal to 90.3) at Handong Global University
Korean, English