AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).
Contributions:15 commits in 1 month
systemverilogtestbenchuvm
Contributions:10 commits, 6 pushes, 1 branch in 1 day