Igor Loi
Senior IC Designer at ACUTE Design
Grenoble, Auvergne-Rhône-Alpes, France
Summary
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Rockstar🎓
Top SchoolIgor Loi is a Senior IC Designer with eight years of hands-on experience driving front-end ASIC development from RTL to GDSII, currently based in Grenoble and recently joining Essilor Group. He has led RTL development, IP integration, verification, synthesis, SDC/UPF and power analysis across three product-grade tape-outs (65nm and multiple FDSOI nodes), and also contributes to backend PnR and STA. His background blends academic research on low-power, low-latency on-chip interconnects and 3D integration with practical IP work on the PULP ecosystem and collaborations with STMicroelectronics, CEA, IMEC and ETH Zurich. Comfortable across Verilog/SystemVerilog/VHDL/SystemC and a wide ASIC toolchain, he pairs algorithmic low-power expertise with detailed physical implementation know-how. A less obvious strength is his track record of moving research concepts (3D NoC, TSV characterization, ultra-low-power multicore techniques) into multiple taped-out silicon platforms.
8 years of coding experience
9 years of employment as a software developer
Doctor of Philosophy (Ph.D.) in Electronic Engineering, Micrellab - DEIS - University of Bologna, Doctor of Philosophy (Ph.D.) in Electronic Engineering, Micrellab - DEIS - University of Bologna at Alma Mater Studiorum – Università di BolognaMaster's degree, Electrical, Electronics and Communications Engineering, Master's degree, Electrical, Electronics and Communications Engineering at Università degli Studi di Cagliari60/60, Electronics and Automations, 60/60, Electronics and Automations at Istituto Tecnico Industriale Statale ITISElectronic Engineering, Electronic Engineering at Stanford University
Italian, English, French
Github Skills (10)
systemverilog9
risc-v9
simulation8
fpga8
floating-point6
sqrt5
pulp2
fifo2
asynchronous1
cdc1
Programming languages (3)
Github contributions (5)
pulp-platform/L2_tcdm_hybrid_interco
Apr 2018 - Aug 2019
Contributions:2 PRs, 9 pushes, 1 branch in 1 year 4 months
pulp-platform/tech_cells_generic
May 2018 - Jul 2019
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Contributions:13 pushes, 7 tags in 1 year 2 months
fpgasimulation
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