Ilya Tuzov
Researcher at Universitat Politècnica de València (UPV)
Valencian Community, Spain
Summary
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Senior🎓
Top SchoolIlya Tuzov is a researcher and FPGA/ASIC design engineer with 8 years of experience specializing in fault-tolerant RISC-V SoC design, dependability benchmarking, and automated verification. He holds a PhD focused on dependability-driven strategies for safety-critical HDL systems and has led development of a fault injection toolkit (DAVOS) and high-speed, bit-accurate fault emulation methods for Xilinx FPGAs. At Universitat Politècnica de València he designs and verifies mitigation mechanisms, performs simulation/emulation of hardware faults, and drives dependability-driven optimization across IP and EDA flows. Known for bridging rigorous research and practical tooling, he has published extensively and built reproducible toolchains that accelerate robustness assessment of FPGA prototypes. Based in the Valencian Community, he combines academic depth with hands-on implementation skills that make safety analysis repeatable and automated.
8 years of coding experience
Master in Software Engineering, Computer Software Engineering, Excellent (A), 120 ECTS, Master in Software Engineering, Computer Software Engineering, Excellent (A), 120 ECTS at Moscow Aviation Institute (National Research University)Universitat Politècnica de València
Russian, German, English, Spanish
Github Skills (2)
hardware8
risc-v7
Programming languages (2)
Github contributions (3)
IlyaTuzov/DAVOS
Apr 2018 - Feb 2023
Toolkit for Dependability assessment, verification, optimization and selection of hardware models
Contributions:75 commits, 76 pushes, 3 branches in 4 years 10 months
hardware
IlyaTuzov/tristan-isolde-unified-access-page
Jul 2025 - Jul 2025
Unified Access Page for the TRISTAN project
Contributions:1 push in 1 day
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