Summary
Jason Glass is a Senior FPGA Design Engineer with 11 years' experience building high-performance hardware and integrating FPGAs into RF systems that handle over 100 Gbps, primarily on Xilinx Ultrascale+ platforms. He has designed PCIe interfaces for neural-network accelerators, led RTL verification and timing work bridging ASIC/FPGA practices, and driven automation of build and regression test flows with Bash, Python and TCL. Experienced at inheriting undocumented C/C++ and VHDL codebases, he pragmatically refactors legacy systems to improve maintainability and performance. Jason has applied his FPGA expertise in niche domains—from cryogenic superconducting testbeds interfacing lab equipment to real-time ADC+FFT pipelines—translating customer requirements into reliable implementations. Based in Oxford, he combines hands-on hardware design with system-level integration skills and a knack for turning messy, poorly documented projects into production-ready solutions.
11 years of coding experience
4 years of employment as a software developer
Bachelor of Science (B.S.), Computer Engineering, 3.09, Bachelor of Science (B.S.), Computer Engineering, 3.09 at Northwestern University
Master of Science - MS, Computer Engineering, 3.5, Master of Science - MS, Computer Engineering, 3.5 at The Graduate School at Northwestern University