Summary
Jianqiao Lv is an SoC design engineer with 10 years’ experience delivering analog and digital ICs across full RTL-to-GDS flows, having taped out 10+ chips and worked hands-on with TSMC 28/16/12/10/7/5 nm and SMIC 40/28/14/7 nm processes. His expertise spans process technology, ESD, latch-up, EM, synthesis, timing closure, and both analog and digital back-end—skills honed at Huawei and now applied at Intel. He combines physical design and verification strengths with scripting and tool development (Python/Shell/Skill) to automate flows and accelerate teams, and has built ELK-based databases for timing and yield analysis. A year of data analysis and auto-test experience, plus a background in game-system testing at NVIDIA, gives him a pragmatic systems perspective beyond pure silicon design. Fluent in engineering and familiar with cross-disciplinary challenges, he also studied Japanese and management, reflecting a blend of technical depth and broader cultural and organizational awareness.
10 years of coding experience
6 years of employment as a software developer
Bachelor of Engineering (B.E.), Electronic Science and Technology, Bachelor of Engineering (B.E.), Electronic Science and Technology at Tongji University
Master of Engineering - MEng, Engineering/Industrial Management, Master of Engineering - MEng, Engineering/Industrial Management at Tsinghua University
Chinese, English, Japanese