Li Xinbing
Design Manager at Shanghai Feiju Microelectronics Co.LTD
Shanghai, Shanghai, China
Summary
👤
Senior🎓
Top SchoolLi Xinbing is a design manager with 11+ years specializing in digital IC and RFID product development, currently leading yield and interface projects at Shanghai Feiju Microelectronics. He has a strong track record across RTL design, verification, FPGA prototyping and low-power synthesis, driving wafer yields from ~70k to over 100k dies and delivering multiple ISO 14443/15693 solutions. Earlier roles span DDR PHY/controller integration, ARM7/8051-based smartcard systems, FFT/IFFT accelerators and cellular baseband blocks, giving him deep system-to-gate expertise. A practical open-source enthusiast who publishes work on GitHub, he combines hands-on RTL coding with cross-disciplinary collaboration between digital, analog and firmware teams.
12 years of coding experience
8 years of employment as a software developer
Master's degree, microelectronics, Master's degree, microelectronics at East China Normal UniversityBachelor's degree, Communication, Bachelor's degree, Communication at Chongqing University of Post and Telecommunications
Github Skills (10)
cpu10
verilog10
805110
uclinux9
risc-v9
modelsim9
32-bit8
fpga8
asic7
linux7
Programming languages (2)
Github contributions (5)
risclite/ARM9-compatible-soft-CPU-core
Oct 2018 - Oct 2020
This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.
Contributions:8 commits, 6 pushes, 1 branch in 2 years
fpgalinuxmodelsimuclinuxverilog
risclite/SuperScalar-RISCV-CPU
May 2019 - Aug 2020
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Contributions:73 commits, 74 pushes, 1 branch in 1 year 3 months
risc-v
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