Summary
Longxiao Li is a Design Lead based in San Jose with nine years of hands-on experience in SoC architecture, RTL design, and ASIC/FPGA implementation across storage and heterogeneous computing domains. He has driven architecture and silicon bring-up for SSD and computational storage products at companies including ByteDance, Alibaba Cloud, ScaleFlux, and Marvell, pairing strong RTL skills in Verilog/SystemVerilog with practical FPGA implementation and timing closure expertise. His domain knowledge spans NAND flash, DDR, and PCIe subsystems, and he complements hardware expertise with C and Python for system-level validation and tooling. Known for bridging architecture and implementation, he often leads cross-functional debug and system bring-up efforts that turn complex storage concepts into production silicon.
9 years of coding experience
9 years of employment as a software developer
Master's, Computer Engineering, Master's, Computer Engineering at Syracuse University
Bachelor's degree, EE, Bachelor's degree, EE at Central South University
English, Chinese