Martin Aigner
Austria
Summary
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Rockstar🎓
Top SchoolMartin Aigner is an experienced Hardware System Engineer with 13 years specializing in multimedia processing for SoCs, fluent across ASIC and FPGA design flows. He brings hands-on expertise in verification and design using VHDL/Verilog/SystemVerilog, UVM, and industry tools like Cadence, ModelSim, QuestaSim and Synopsys Design Compiler. Comfortable bridging algorithm and silicon, he also applies deep learning toolchains—TensorFlow, Keras and OpenVINO—toward hardware-accelerated inference. Used to collaborating in geographically and culturally dispersed teams, he combines methodical engineering with practical system-level thinking. Trained at University of Applied Sciences Upper Austria (Hagenberg), he pairs academic grounding with long-term, production-focused delivery. An engineer who moves seamlessly between MATLAB/Simulink prototyping and RTL implementation, he’s adept at turning complex multimedia concepts into verifiable silicon-ready designs.
13 years of coding experience
Bachelor's degree, Bachelor's degree at University of Applied Sciences Upper Austria - Hagenberg Campus
English, German
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (17)
benchmarking9
virtual-machine9
symbolic-execution-engine9
multicore9
hypervisor8
profiling8
c-compiler8
risc-v7
compiler6
computer-science6
operating-system6
react6
java6
allocator5
cprogramming-language5
Programming languages (3)
Github contributions (5)
cksystemsteaching/SE-Winter-2015
Oct 2015 - Dec 2015
Systems Engineering 2015
Contributions:10 commits, 4 PRs, 10 pushes in 2 months
reactengineeringjavareactjssystems-engineering
cksystemsgroup/ACDC
Dec 2012 - Aug 2016
A multi-threaded mutator for profiling and benchmarking heap management systems
Contributions:314 commits, 12 pushes, 2 tags in 3 years 8 months
benchmarkingprofiling
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