Maurizio Palesi
Professor at Università di Catania
Catania, Sicily, Italy
Summary
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SeniorMaurizio Palesi is a Professor and embedded systems researcher based in Catania, Sicily, with a focus on single-chip system-on-a-chip (SoC) design and eight years of professional experience. His expertise spans instruction-level power modeling, multi-objective optimization, design-space exploration of parameterized SoC platforms, low-power design, and Network-on-Chip architectures. He combines rigorous academic inquiry with practical engineering aimed at enabling complete embedded systems for domains from automotive and aerospace to telecommunications and medical devices. Known for tackling cross-layer challenges, he brings particular strength in modeling and optimizing trade-offs between power, performance, and on-chip communication.
9 years of coding experience
English, Italian
Github Skills (8)
network-analysis9
simulation9
4g8
openflow8
systemc8
simulator7
communications6
neural-network4
Programming languages (1)
Github contributions (4)
mpalesi/nocnn
Jun 2019 - Jul 2020
Performance/Energy estimation of NoC-based Deep Neural Network accelerators
Contributions:13 commits, 1 PR, 11 pushes in 1 year 1 month
neural-network
mpalesi/qcomm
Jan 2024 - Nov 2025
Contributions:47 pushes, 6 branches, 1 tag in 1 year 10 months
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