Meher Chakka is a Senior Silicon Design Engineer with 11 years in chip design and verification, currently driving SERDES DV at AMD after multi-role experience at Samsung Semiconductor. She brings deep SoC verification expertise—particularly in image sensor subsystems, NVM/OTP controllers, and serial/AMBA protocols—combined with hands-on CPU/firmware test methodologies and Cadence tool proficiency. Known for automating verification flows via scripting, she bridges low-level hardware behavior and scalable verification infrastructure. Her background combines an ECE degree from VIT with a progression from intern to associate staff engineer, reflecting rapid technical growth and ownership. Colleagues value her pragmatic approach to complex protocol validation and her ability to translate firmware-driven scenarios into robust silicon-level tests.
11 years of coding experience
4 years of employment as a software developer
BITS Pilani, Birla Institute of Technology and Science
Bachelor of Technology Electrical, Electronics and Communications Engineering, Bachelor of Technology Electrical, Electronics and Communications Engineering at Vellore Institute of Technology
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