Summary
Ming-yen Kao is a Staff Hardware Engineer at NVIDIA with eight years of experience bridging device physics, compact modeling, and VLSI physical-design methodology. He holds a PhD from UC Berkeley where he developed NCFET compact models, built TCAD-integrated simulators, and applied Monte Carlo and deep-learning techniques for parameter extraction and variability analysis. At NVIDIA he advanced STA methodology with ML-driven fast recharacterization and timing models that account for PVT, process drift, aging, and self‑heating. His background spans top-tier research and production ASIC flows, uniquely combining hands-on device simulation and modeling with practical CAD tool development. A high-achieving graduate of National Taiwan University, he often applies data-driven methods to classical device problems, reflecting a rare blend of semiconductor physics and machine-learning tooling. Based in New Taipei, Taiwan, he brings both academic rigor and production-grade engineering to scaling next-generation transistor and timing methodologies.
9 years of coding experience
1 year of employment as a software developer
Master of Science - MS, Electrical and Electronics Engineering, 3.9/4.0, Master of Science - MS, Electrical and Electronics Engineering, 3.9/4.0 at University of California, Berkeley
Bachelor of Science (B.S.), Electrical Engineering, 4.14/4.3, Bachelor of Science (B.S.), Electrical Engineering, 4.14/4.3 at National Taiwan University
Chinese, English