Simon Southwell
Retired
Cambridge, England, United Kingdom
Summary
🤩
Rockstar🎓
Top SchoolSimon Southwell is a semi-retired engineer with over 35 years of R&D experience specializing in ASIC, FPGA and embedded software design, now focused on open-source IP and mentoring. His career spans high-performance computing, cellular and wireless systems, processor/subsystem design, verification and co-simulation, with hands-on work in PCIe, data compression logic and SoC modelling. A long history of roles from Hewlett-Packard to u‑blox and BlackBerry reflects deep practical experience across both silicon and firmware domains. He is an active collaborator on the OSVVM project, extending co-simulation capabilities and sharing tools for the community. Based in Cambridge, he balances selective consulting and contributions with writing technical articles and guiding junior engineers. Less obvious: his background in supercomputing architectures informs a systems-level perspective that efficiently bridges algorithmic, hardware and verification concerns.
10 years of coding experience
29 years of employment as a software developer
BSc (1st Hons), BSc (1st Hons) at University of the West of EnglandMSc, MSc at University of Bristol
Github Skills (58)
verilog10
systemverilog10
pli10
dpi10
codesign10
risc-v10
verification10
vhdl10
verilator10
pci10
ghdl10
vpi10
co-simulation10
fpga10
pcie10
Programming languages (6)
Github contributions (5)
wyvernSemi/mem_model
Aug 2021 - Feb 2026
High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model
Contributions:29 pushes, 1 branch, 1 tag in 4 years 6 months
co-simulationcppmemory-modelverilogvhdl
wyvernSemi/vproc
Sep 2016 - Aug 2021
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus
Contributions:1 release, 35 commits, 1 PR in 4 years 11 months
co-simulationsimulationsystemverilogverilogvhdl
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