Steven Herbst
Member Of Technical Staff at OpenAI
Mountain View, California, United States
Summary
🤩
Rockstar🎓
Top SchoolSteven Herbst is a Member of Technical Staff at OpenAI with 17 years of experience bridging hardware, FPGA acceleration, and systems-level software. He has led engineering teams to build cloud FPGA-based emulation and web-deployed chiplet system tools as Director of Software Solutions at Zero ASIC, and previously served as CTO of an autonomous robotics startup focused on sustainable farming. His PhD work at Stanford produced open-source FPGA emulation tools that accelerated mixed-signal chip simulation by two to three orders of magnitude, reflecting a strong research-to-product track record. Earlier roles include hardware design contributions at Apple (first-gen Apple Watch charger) and analog/PMIC work at Intersil, giving him a rare combination of silicon, embedded systems, and cloud deployment expertise. Based in Mountain View, he brings product-minded leadership to complex cross-disciplinary problems, often turning academic breakthroughs into practical developer-facing tools.
18 years of coding experience
7 years of employment as a software developer
Master of Engineering (M.Eng.), Electrical Engineering and Computer Science, Master of Engineering (M.Eng.), Electrical Engineering and Computer Science at Massachusetts Institute of TechnologyDoctor of Philosophy (PhD), Electrical Engineering, Doctor of Philosophy (PhD), Electrical Engineering at Stanford University
Github Skills (84)
verilog10
parser10
python10
iverilog10
synthesis10
instantiation10
fixed-point10
floating-point10
emulation10
high-speed10
icarus10
fpga10
vivado10
logic10
systemverilog10
Programming languages (7)
Github contributions (5)
sgherbst/sky130-hello-world
Dec 2020 - Jan 2021
Minimal SKY130 example with self-checking LVS, DRC, and PEX
Contributions:34 commits, 1 PR, 33 pushes in 1 month
pexdrccheckingsky130lvs
sgherbst/pysvinst
Mar 2020 - Apr 2021
Python library for parsing module definitions and instantiations from SystemVerilog files
Contributions:1 review, 89 commits, 15 PRs in 1 year 2 months
parsingpythonsystemverilogverilogparser
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