Tuo Li
Associate Professor
Beijing, China
Summary
👤
Senior🎓
Top SchoolTuo Li is an associate professor and researcher with eight years of experience focused on reliable and secure computer architecture, particularly timing-channel mitigation and memory safety on RISC-V platforms. He led the design and FPGA prototyping of mechanisms such as SIMF, FaSe, SHORE, and HWST128, demonstrating practical implementations on Rocket Chip running Linux and seL4. His work bridges academic research and hands-on system engineering, with deployments on Xilinx ZCU102 and evaluations using riscv-pk and SPEC benchmarks. Having contributed to international projects on trustworthy platforms and dependable embedded systems, he combines deep processor-level expertise with a track record of building verifiable, deployable prototypes. An experienced PhD-trained engineer who moved from UNSW research roles to a faculty position at the Chinese Academy of Sciences, he often focuses on threats that are subtle in hardware yet critical for system security.
9 years of coding experience
9 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Computer Science, Doctor of Philosophy (Ph.D.), Computer Science at University of New South WalesBachelor of Electrical Engineering, Bachelor of Electrical Engineering at Hefei University of Technology
English, Chinese
Github Skills (19)
zynqmp10
zynq10
vivado10
risc-v9
xilinx9
rocket-chip9
fpga9
cufft8
linear-algebra7
chisel7
scala7
instruction-set7
trust7
cuda6
gpu6
Programming languages (5)
Github contributions (5)
li3tuo4/rc-zcu102-tutorial
Jan 2019 - May 2021
Contributions:10 commits, 1 PR, 9 pushes in 2 years 3 months
li3tuo4/rc-fpga-zcu
Jul 2018 - Nov 2021
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
Contributions:32 commits, 28 pushes, 1 branch in 3 years 3 months
fpgarocket-chipxilinxzynqfpga-board
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