Uwe Simm
Solution Architect Verification
Munich, Bavaria, Germany
Summary
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SeniorUwe Simm is a Solution Architect Verification with 15 years’ experience driving hardware verification adoption and complex pre-sales and customer programs at Cadence from Munich. As a UVM technical lead he owns UVM development and adjacent tool flows, blending deep expertise in eRM/OVM/UVM, Specman/SystemVerilog, and HDL RTL (VHDL/Verilog) with software design skills (UML, AOP, OOP, patterns). He routinely architects cross-domain verification solutions and pilots leading-edge customer projects that feed back into R&D and methodology development. Known for translating high-level verification strategy into practical, deployable environments, he supports engagements from initial planning through successful delivery. His work sits at the intersection of tooling, methodology, and hands-on verification, enabling customers to scale modern verification flows. Colleagues rely on him for pragmatic innovation and for bridging gaps between product engineering and field requirements.
16 years of coding experience
Github Skills (57)
rocket9
uvm9
systemverilog9
full-stack9
unified-diffs8
vue8
nuxt8
rust7
currency-converter7
z37
vaultwarden7
docker7
frontend7
currency-exchange-rates6
exposure-notification6
Programming languages (10)
Github contributions (5)
uwesimm/uvm-indirect-registers
Feb 2017 - Nov 2017
Contributions:7 commits, 2 pushes, 1 branch in 8 months
Freecellera/freecellera-uvm
Aug 2010 - Nov 2014
Freecellera fork of the Universal Verification Methodology (SystemVerilog verification library from Accellera.org)
Contributions:585 commits in 4 years 3 months
systemveriloguvm
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