Summary
Yashasvi Khatavkar is a Senior Compiler Software Engineer with four years of experience building and maintaining compilers and language tooling at Intel, after earlier compiler work at Cadence. He brings deep C/C++ and object-oriented design skills applied to parser implementation, regression maintenance, and memory-leak remediation for complex system-level languages like SystemVerilog. His background blends embedded firmware and research—developing UWB-based intelligent rail systems and prototyping BLE-enabled devices—giving him a practical hardware-aware perspective on compiler and tooling problems. At Intel he progressed from compiler engineer to senior contributor, demonstrating rapid impact in a rigorous, performance-sensitive codebase. Colleagues rely on him for high-quality bug fixes and pragmatic design choices that balance correctness, performance, and maintainability. He holds an M.S. in Electrical and Computer Engineering from Rutgers and often bridges low-level system constraints with higher-level language implementation decisions.
4 years of coding experience
6 years of employment as a software developer
Bachelor of Technology Electrical Electronics and Communications Engineering, Bachelor of Technology Electrical Electronics and Communications Engineering at CHARUSAT
Master's degree electrical and computer engineering, Master's degree electrical and computer engineering at Rutgers University
English, Hindi, Marathi, Gujarati, Tamil