Yue Yang
Graduate Student Researcher
Fresno, California, United States
Summary
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Senior🎓
Top SchoolYue Yang is an M.S. electrical and computer engineering student at CSU Fresno with eight years of engineering experience and a 4.0 GPA, specializing in VLSI/ASIC design, physical design, and hardware–software codesign. She has published multiple IEEE conference papers (one as first author) and is Cadence RTL-to-GDS certified, with hands-on expertise spanning Verilog, C/C++, Python, Tcl, FPGA, and advanced-node physical design workflows. Her recent work designs a SIMD-based many-core accelerator for INT8/INT16 matrix multiplication targeted at generative AI edge applications, which she is scaling into a full-stack system thesis and presenting at IEEE SoC 2025. A seasoned teaching assistant and mentor, she has led high-participation supplemental instruction programs and served as SWE chapter president, demonstrating strong communication and leadership alongside technical depth. Her background switching from GIS and software engineering to VLSI uniquely equips her to bridge algorithmic, system-level, and device-aware perspectives in semiconductor design.
8 years of coding experience
3 years of employment as a software developer
Bachelor's degree, Geographic Information Systems (GIS), Bachelor's degree, Geographic Information Systems (GIS) at Yangtze UniversityUncompleted Master's degree; missed thesis due to travel restrictions during the pandemic, Software Engineering, Uncompleted Master's degree; missed thesis due to travel restrictions during the pandemic, Software Engineering at China University of GeosciencesMaster of Science - MS, Electrical and computer engineering, Master of Science - MS, Electrical and computer engineering at California State University, Fresno
English, ChineseGithub contributions (5)
hoshinotsuki/leetcodeSolution
Feb 2019 - Apr 2019
Contributions:184 commits, 117 pushes, 3 branches in 1 month
hoshinotsuki/hoshinotsuki.github.io
Mar 2019 - Apr 2019
Contributions:68 pushes, 1 branch in 23 days
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